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1 ltc1430 high power step-down switching regulator controller the ltc ? 1430 is a high power, high efficiency switching regulator controller optimized for 5v to 3.xv applications. it includes a precision internal reference and an internal feedback system that can provide output regulation of 1% over temperature, load current and line voltage shifts. the ltc1430 uses a synchronous switching architecture with two n-channel output devices, eliminating the need for a high power, high cost p-channel device. additionally, it senses output current across the drain-source resistance of the upper n-channel fet, providing an adjustable current limit without an external low value sense resistor. the ltc1430 includes a fixed frequency pwm oscillator for low output ripple under virtually all operating conditions. the 200khz free-running clock frequency can be externally adjusted from 100khz to above 500khz. the ltc1430 features low 350 m a quiescent current, allowing greater than 90% efficiency operation in converter designs from 1a to greater than 50a output current. shutdown mode drops the ltc1430 supply current to 1 m a. for new designs, refer to the ltc3830 . n high power 5v to 3.xv switching controller: can exceed 10a output n all n-channel external mosfets n constant frequency operationsmall inductor n excellent output regulation: 1% over line, load and temperature variations n high efficiency: over 95% possible n fixed frequency operation n no low value sense resistor needed n outputs can drive external fets with up to 10,000pf gate capacitance n quiescent current: 350 m a typ, 1 m a in shutdown n fast transient response n adjustable or fixed 3.3v output n available in 8- and 16-lead pdip and so packages , ltc and lt are registered trademarks of linear technology corporation. load current (a) 40 70 100 90 80 50 60 efficiency (%) 10 ltc1430 ?ta02 0.1 1 t a = 25 c v in = 5v v out = 3.3v efficiency + c in 220 m f 4 c out 330 m f 6 + + + l1, 2.8 m h pv cc1 v cc freqset shdn comp ss pv cc2 pgnd gnd g1 i fb i max g2 nc ltc1430 ?ta01 shutdown fb nc c in : avx-tpse227m010r0100 c out : avx-tpse337m006r0100 l1: etqp6f1r6sfa m1a, m1b, m2: motorola mtd20n03hl sense + ltc1430 sense 16k 100 w r c 7.5k c c 4700pf c1 220pf 1n4148 1k 0.1 m f 1 m f 0.01 m f 0.1 m f 4.7 m f 0.1 m f 3.3v 10a m1a, m1b 2 in parallel m2 v in 5v typical 5v to 3.3v, 10a application n power supply for p6 and pentium ? microprocessors n high power 5v to 3.xv regulators n local regulation for dual voltage logic boards n low voltage, high current battery regulation pentium is a registered trademark of intel corporation. applicatio s u features typical applicatio u descriptio u
2 ltc1430 supply voltage v cc ....................................................................... 9v pv cc1, 2 .............................................................. 13v input voltage i fb ......................................................... C 0.3v to 18v all other inputs ...................... C 0.3v to (v cc + 0.3v) operating temperature range ltc1430c .............................................. 0 c to 70 c ltc1430i ........................................... C 40 c to 85 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c order part number order part number ltc1430cn ltc1430cs ltc1430is ltc1430cn8 ltc1430cs8 s8 part marking 1430 symbol parameter conditions min typ max units v cc supply voltage l 48v pv cc pv cc1 , pv cc2 l 13 v v out output voltage figure 1 l 3.30 v v fb feedback voltage figure 1, sense + and sense C floating (ltc1430c) l 1.25 1.265 1.28 v figure 1, sense + and sense C floating (ltc1430i) l 1.23 1.265 1.29 v d v out output load regulation figure 1, i out = 0a to 10a (note 3) (ltc1430c) l 520 mv figure 1, i out = 0a to 10a (note 3) (ltc1430i) 5 mv output line regulation figure 1, v cc = 4.75v to 5.25v (note 3) (ltc1430c) l 15 mv figure 1, v cc = 4.75v to 5.25v (note 3) (ltc1430i) 1 mv iv cc supply current (v cc only) figure 2, v shdn = v cc l 350 700 m a v shdn = 0v 1 10 m a ipv cc supply current (pv cc ) figure 2, pv cc = 5v, v shdn = v cc (note 4) 1.5 ma v shdn = 0v 0.1 m a f osc internal oscillator frequency freqset floating (ltc1430c) l 140 200 260 khz freqset floating (ltc1430i) l 130 200 300 khz the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 5v unless otherwise noted. (note 2) consult factory for industrial and military grade parts. t jmax = 150 c, q ja = 100 c/w (n8) t jmax = 150 c, q ja = 150 c/w (s8) 1 2 3 4 8 7 6 5 top view g1 pv cc1 gnd fb g2 v cc /pv cc2 comp shdn n8 package 8-lead pdip s8 package 8-lead plastic so t jmax = 150 c, q ja = 70 c/w (n) t jmax = 150 c, q ja = 110 c/w (s) 1 2 3 4 5 6 7 8 top view s package 16-lead plastic so n package 16-lead pdip 16 15 14 13 12 11 10 9 g1 pv cc1 pgnd gnd sense fb sense + shdn g2 pv cc2 v cc i fb i max freqset comp ss (note 1) absolute axi u rati gs w ww u package/order i for atio uu w electrical characteristics
3 ltc1430 symbol parameter conditions min typ max units note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to ground unless otherwise specified. note 3: this parameter is guaranteed by correlation and is not tested directly. note 4: supply current in normal operation is dominated by the current needed to charge and discharge the external fet gates. this will vary with the ltc1430 operating frequency, operating voltage and the external fets used. note 5: the i lim amplifier can sink but cannot source current. under normal (not current limited) operation, the i lim output current will be zero. the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 5v unless otherwise noted. (note 2) electrical characteristics v ih shdn input high voltage l 2.4 v v il shdn input low voltage l 0.8 v i in shdn input current l 0.1 1 m a a v error amplifier open-loop dc gain (ltc1430i) l 40 48 db gm v error amplifier transconductance (ltc1430c) 650 m mho (ltc1430i) l 300 650 1200 m mho gm i i lim amplifier transconductance (note 5) 1300 m mho i max i max sink current v i(max) = v cc (ltc1430c) l 81216 m a v i(max) = v cc (ltc1430i) l 81217 m a i ss soft-start source current v ss = 0 (ltc1430c) l C8 C12 C16 m a v ss = 0 (ltc1430i) l C8 C12 C17 m a t r , t s driver rise/fall time figure 3, pv cc1 = pv cc2 = 5v 80 250 ns t nov driver non-overlap time figure 3, pv cc1 = pv cc2 = 5v 25 130 250 ns dc max maximum duty cycle v comp = v cc (ltc1430c) l 90 96 % v comp = v cc , v fb = 0 (ltc1430i) l 90 96 % v comp = v cc , v fb = 1.265v (ltc1430i) l 83 88 %
4 ltc1430 g1 (pin 1/pin 1): driver output 1. connect this pin to the gate of the upper n-channel mosfet, m1. this output will swing from pv cc1 to pgnd. it will always be low when g2 is high. pv cc1 (pin 2/pin 2): power v cc for driver 1. this is the power supply input for g1. g1 will swing from pgnd to pv cc1 . pv cc1 must be connected to a potential of at least pv cc + v gs(on) (m1). this potential can be generated using an external supply or a simple charge pump con- nected to the switching node between the upper mosfet and the lower mosfet; see applications information for details. pgnd (pin 3/pin 3): power ground. both drivers return to this pin. it should be connected to a low impedance ground in close proximity to the source of m2. 8-lead parts have pgnd and gnd tied together at pin 3. gnd (pin 4/pin 3): signal ground. all low power internal circuitry returns to this pin. to minimize regulation errors due to ground currents, gnd should be connected to pgnd right at the ltc1430. 8-lead parts have pgnd and gnd tied together internally at pin 3. sense C , fb, sense + (pins 5, 6, 7/pin 4): these three pins connect to the internal resistor divider and to the internal feedback node. to use the internal divider to set the output voltage to 3.3v, connect sense + to the positive terminal of the output capacitor and sense C to the nega- tive terminal. fb should be left floating in applications that use the internal divider. to use an external resistor divider to set the output voltage, float sense + and sense C and connect the external resistor divider to fb. shdn (pin 8/pin 5): shutdown. a ttl compatible low level at shdn for longer than 50 m s puts the ltc1430 into shutdown mode. in shutdown, g1 and g2 go low, all internal circuits are disabled and the quiescent current drops to 10 m a max. a ttl compatible high level at shdn allows the part to operate normally. ss (pin 9/na): soft-start. the ss pin allows an external capacitor to be connected to implement a soft-start func- tion. an external capacitor from ss to ground controls the start-up time and also compensates the current limit loop, allowing the ltc1430 to enter and exit current limit cleanly. see applications information for more details. comp (pin 10/pin 6): external compensation. the comp pin is connected directly to the output of the error amplifier and the input of the pwm. an rc network is used at this node to compensate the feedback loop to provide opti- mum transient response. see applications information for compensation details. freqset (pin 11/na): frequency set. this pin is used to set the free running frequency of the internal oscillator. with the pin floating, the oscillator runs at about 200khz. a resistor from freqset to ground will speed up the oscillator; a resistor to v cc will slow it down. see applica- tions information for resistor selection details. i max (pin 12/na): current limit set. i max sets the thresh- old for the internal current limit comparator. if i fb drops below i max with g1 on, the ltc1430 will go into current limit. i max has a 12 m a pull-down to gnd. it can be adjusted with an external resistor to pv cc or an external voltage source. i fb (pin 13/na): current limit sense. connect to the switched node at the source of m1 and the drain of m2 through a 1k resistor. the 1k resistor is required to prevent voltage transients from damaging i fb . this pin can be taken up to 18v above gnd without damage. v cc (pin 14/pin 7): power supply. all low power internal circuits draw their supply from this pin. connect to a clean power supply, separate from the main pv cc supply at the drain of m1. this pin requires a 4.7 m f bypass capacitor. 8-lead parts have v cc and pv cc2 tied together at pin 7 and require a 10 m f bypass to gnd. pv cc2 (pin 15/pin 7): power v cc for driver 2. this is the power supply input for g2. g2 will swing from gnd to pv cc2 . pv cc2 is usually connected to the main high power supply. the 8-lead parts have v cc and pv cc2 tied together at pin 7 and require a 10 m f bypass to gnd. g2 (pin 16/pin 8): driver output 2. connect this pin to the gate of the lower n-channel mosfet, m2. this output will swing from pv cc2 to pgnd. it will always be low when g1 is high. (16-lead package/8-lead package) pi fu ctio s uuu
5 ltc1430 + + i lim fb min pwm max + 40mv 20.1k + 1.26v 12 m a + 40mv 12 m a 12.4k pv cc1 shdn freqset comp ss i max v cc pv cc2 g1 g2 pgnd i fb fb sense + sense ltc1430 ?bd internal shutdown 50 m s delay block diagra w figure 1 figure 2 figure 3 ltc1430 pv cc1 5v v cc pv cc2 gnd pgnd g1 rise/fall g2 rise/fall g1 g2 10,000pf ltc1430 ?tc03 10,000pf 10 m f 0.1 m f shdn v shdn i max freqset comp ss nc nc nc nc v cc pv cc2 ltc1430 pv cc pv cc1 i fb gnd pgnd sense + sense ltc1430 ?tc02 g1 g2 fb nc nc nc v cc + c in 220 m f 4 c out 330 m f 6 + + + 2.7 m h/15a pv cc1 v cc freqset shdn comp ss pv cc2 pv cc = 5v pgnd gnd g1 i fb i max g2 nc ltc1430 ?f01 shutdown fb nc sense + ltc1430 sense 1.61k 1k fb nc nc sense + sense ltc1430 fb measurement v out 100 w r c 7.5k c c 4700pf c1 220pf 1n4148 1 m f 0.01 m f 0.1 m f 4.7 m f 0.1 m f 3.3v m1a, m1b 2 in parallel m2 m1a, m1b, m2: motorola mtd20n03hl c in : avx-tpse227m010r0100 c out : avx-tpse337m006r0100 test circuits
6 ltc1430 overview the ltc1430 is a voltage feedback pwm switching regu- lator controller (see block diagram) designed for use in high power, low voltage step-down (buck) converters. it includes an onboard pwm generator, a precision refer- ence trimmed to 0.5%, two high power mosfet gate drivers and all necessary feedback and control circuitry to form a complete switching regulator circuit. the pwm loop nominally runs at 200khz. the 16-lead versions of the ltc1430 include a current limit sensing circuit that uses the upper external power mosfet as a current sensing element, eliminating the need for an external sense resistor. also included in the 16-lead version is an internal soft- start feature that requires only a single external capacitor to operate. in addition, 16-lead parts feature an adjustable oscillator which can run at frequencies from 50khz to beyond 500khz, allowing added flexibility in external com- ponent selection. the 8-lead versions do not include current limit, internal soft-start or frequency adjustability. theory of operation primary feedback loop the ltc1430 senses the output voltage of the circuit at the output capacitor with the sense + and sense C pins and feeds this voltage back to the internal transconductance amplifier fb. fb compares the resistor-divided output voltage to the internal 1.26v reference and outputs an error signal to the pwm comparator. this is then com- pared to a fixed frequency sawtooth waveform generated by the internal oscillator to generate a pulse width modu- lated signal. this pwm signal is fed back to the external mosfets through g1 and g2, closing the loop. loop compensation is achieved with an external compensation network at comp, the output node of the fb transconduc- tance amplifier. min, max feedback loops two additional comparators in the feedback loop provide high speed fault correction in situations where the fb amplifier may not respond quickly enough. min compares the feedback signal to a voltage 40mv (3%) below the internal reference. at this point, the min comparator overrides the fb amplifier and forces the loop to full duty cycle, set by the internal oscillator at about 90%. similarly, the max comparator monitors the output voltage at 3% above the internal reference and forces the output to 0% duty cycle when tripped. these two comparators prevent extreme output perturbations with fast output transients, while allowing the main feedback loop to be optimally compensated for stability. current limit loop the 16-lead ltc1430 devices include yet another feed- back loop to control operation in current limit. the current limit loop is disabled in 8-lead devices. the i lim amplifier monitors the voltage drop across external mosfet m1 with the i fb pin during the portion of the cycle when g1 is high. it compares this voltage to the voltage at the i max pin. as the peak current rises, the drop across m1 due to its r ds(on) increases. when i fb drops below i max , indicating that m1s drain current has exceeded the maximum level, i lim starts to pull current out of the external soft-start capacitor, cutting the duty cycle and controlling the output current level. at the same time, the i lim comparator generates a signal to disable the min comparator to prevent it from conflicting with the current limit circuit. if the internal feedback node drops below about 0.8v, indi- cating a severe output overload, the circuitry will force the internal oscillator to slow down by a factor of as much as 100. if desired, the turn on time of the current limit loop can be controlled by adjusting the size of the soft-start capacitor, allowing the ltc1430 to withstand short over- current conditions without limiting. by using the r ds(on) of m1 to measure the output current, the current limit circuit eliminates the sense resistor that would otherwise be required and minimizes the number of components in the external high current path. because power mosfet r ds(on) is not tightly controlled and varies with temperature, the ltc1430 current limit is not de- signed to be accurate; it is meant to prevent damage to the power supply circuitry during fault conditions. the actual current level where the limiting circuit begins to take effect may vary from unit to unit, depending on the power mosfets used. see soft-start and current limit for more details on current limit operation. applicatio s i for atio wu u u
7 ltc1430 mosfet gate drive gate drive for the top n-channel mosfet m1 is supplied from pv cc1 . this supply must be above pv cc ( the main power supply input) by at least one power mosfet v gs(on) for efficient operation. an internal level shifter allows pv cc1 to operate at voltages above v cc and pv cc , up to 13v maximum. this higher voltage can be supplied with a separate supply, or it can be generated using a simple charge pump as shown in figure 4. when using a separate pv cc1 supply, the pv cc input may exhibit a large inrush current if pv cc1 is present during power up. the 90% maximum duty cycle ensures that the charge pump will always provide sufficient gate drive to m1. gate drive for the bottom mosfet m2 is provided through pv cc2 for 16-lead devices or v cc /pv cc2 for 8-lead devices. pv cc2 can usually be driven directly from pv cc with 16-lead parts, although it can also be charge pumped or connected to an alternate supply if desired. the 8-lead parts require an rc filter from pv cc to ensure proper operation; see input supply considerations. external component selection power mosfets two n-channel power mosfets are required for most ltc1430 circuits. these should be selected based prima- rily on threshold and on-resistance considerations; ther- mal dissipation is often a secondary concern in high efficiency designs. required mosfet threshold should be determined based on the available power supply voltages and/or the complexity of the gate drive charge pump scheme. in 5v input designs where an auxiliary 12v supply is available to power pv cc1 and pv cc2 , standard mosfets with r ds(on) specified at v gs = 5v or 6v can be used with good results. the current drawn from this supply varies with the mosfets used and the ltc1430s operating frequency, but is generally less than 50ma. ltc1430 designs that use a doubler charge pump to generate gate drive for m1 and run from pv cc voltages below 7v cannot provide enough gate drive voltage to fully enhance standard power mosfets. when run from 5v, a doubler circuit may work with standard mosfets, but the mosfet r on may be quite high, raising the dissipation in the fets and costing efficiency. logic level fets are a better choice for 5v pv cc systems; they can be fully enhanced with a doubler charge pump and will operate at maximum efficiency. doubler designs running from pv cc voltages near 4v will begin to run into efficiency problems even with logic level fets; such designs should be built with tripler charge pumps (see figure 5) or with newer, super low threshold mosfets. note that doubler charge pump designs running from more than 7v and all tripler charge pump designs should include a zener clamp diode d z at pv cc1 to prevent transients from exceeding the absolute maximum rating at that pin. applicatio s i for atio wu u u figure 4. doubling charge pump d z 12v 1n5242 1n5817 1n5817 ltc1430 pv cc1 pv cc2 0.1 m f 10 m f m1 l1 m2 g1 g2 pv cc c out v out ltc1430 ?f05 + 0.1 m f 1n5817 figure 5. tripling charge pump d z 12v 1n5242 optional use for pv cc 3 7v ltc1430 pv cc1 pv cc2 1n4148 m1 l1 m2 g1 g2 pv cc c out v out ltc1430 ?f04 + 0.1 m f
8 ltc1430 once the threshold voltage has been selected, r on should be chosen based on input and output voltage, allowable power dissipation and maximum required output current. in a typical ltc1430 buck converter circuit operating in continuous mode, the average inductor current is equal to the output load current. this current is always flowing through either m1 or m2 with the power dissipation split up according to the duty cycle: dc m v v dc m v v vv v out in out in in out in () () 1 21 = =- = - () the r on required for a given conduction loss can now be calculated by rearranging the relation p = i 2 r: rm pm dc m i vp m vi on max max in max out max () () () () 1 1 1 1 2 2 = = rm pm dc m i vp m vv i on max max in max in out max () () () () 2 2 2 2 2 2 = = - () p max should be calculated based primarily on required efficiency. a typical high efficiency circuit designed for 5v in, 3.3v at 10a out might require no more than 3% efficiency loss at full load for each mosfet. assuming roughly 90% efficiency at this current level, this gives a p max value of (3.3v ? 10a/0.9) ? 0.03 = 1.1w per fet and a required r on of: rm vw va rm vw vva on on () . . . () . . . 1 511 33 10 0 017 2 511 533 10 0 032 2 2 = =w = - () =w note that the required r on for m2 is roughly twice that of m1 in this example. this application might specify a single 0.03 w device for m2 and parallel two more of the same devices to form m1. note also that while the required r on values suggest large mosfets, the dissipation numbers are only 1.1w per device or lesslarge to-220 packages and heat sinks are not necessarily required in high effi- ciency applications. siliconix si4410dy (in so-8) and motorola mtd20n03hl (in dpak) are two small, surface mount devices with r on values of 0.03 w or below with 5v of gate drive; both work well in ltc1430 circuits with up to 10a output current. a higher p max value will generally decrease mosfet cost and circuit efficiency and increase mosfet heat sink requirements. inductor the inductor is often the largest component in an ltc1430 design and should be chosen carefully. inductor value and type should be chosen based on output slew rate require- ments and expected peak current. inductor value is prima- rily controlled by the required current slew rate. the maximum rate of rise of the current in the inductor is set by its value, the input-to-output voltage differential and the maximum duty cycle of the ltc1430. in a typical 5v to 3.3v application, the maximum rise time will be: 90 153 % . - () = m vv l amps second a s i l in out where l is the inductor value in m h. a 2 m h inductor would have a 0.76a/ m s rise time in this application, resulting in a 6.5 m s delay in responding to a 5a load current step. during this 6.5 m s, the difference between the inductor current and the output current must be made up by the output capaci- tor, causing a temporary droop at the output. to minimize this effect, the inductor value should usually be in the 1 m h to 5 m h range for most typical 5v to 3.xv ltc1430 circuits. different combinations of input and output voltages and expected loads may require different values. once the required value is known, the inductor core type can be chosen based on peak current and efficiency requirements. peak current in the inductor will be equal to the maximum output load current added to half the peak- to- peak inductor ripple current. ripple current is set by the applicatio s i for atio wu u u
9 ltc1430 value equal to i out /2. a low esr input capacitor with an adequate ripple current rating must be used to ensure reliable operation. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours (3 months) lifetime; further derating of the input capacitor ripple current beyond the manufacturers specification is recommended to extend the useful life of the circuit. the output capacitor in a buck converter sees much less ripple current under steady-state conditions than the input capacitor. peak-to-peak current is equal to that in the inductor, usually a fraction of the total load current. output capacitor duty places a premium not on power dissipation but on esr. during an output load transient, the output capacitor must supply all of the additional load current demanded by the load until the ltc1430 can adjust the inductor current to the new value. esr in the output capacitor results in a step in the output voltage equal to the esr value multiplied by the change in load current. a 5a load step with a 0.05 w esr output capacitor will result in a 250mv output voltage shift; this is a 7.6% output voltage shift for a 3.3v supply! because of the strong relationship between output capacitor esr and output load transient response, the output capacitor is usually chosen for esr, not for capacitance value; a capacitor with suitable esr will usually have a larger capacitance value than is needed to control steady-state output ripple. electrolytic capacitors rated for use in switching power supplies with specified ripple current ratings and esr can be used effectively in ltc1430 applications. os-con electrolytic capacitors from sanyo give excellent perfor- mance and have a very high performance/size ratio for an electrolytic capacitor. surface mount applications can use either electrolytic or dry tantalum capacitors. tantalum capacitors must be surge tested and specified for use in switching power supplies; low cost, generic tantalums are known to have very short lives followed by explosive deaths in switching power supply applications. avx tps series surface mount devices are popular tantalum capaci- tors that work well in ltc1430 applications. a common way to lower esr and raise ripple current capability is to parallel several capacitors. a typical ltc1430 application might require an input capacitor with a 5a ripple current capacity and 2% output shift with a 10a output load step, which requires a 0.007 w output capacitor esr. sanyo inductor value, the input and output voltage and the operating frequency. if the efficiency is high and can be approximately equal to 1, the ripple current is approxi- mately equal to: d= - () = i vv fl dc dc v v in out osc out in f osc = ltc1430 oscillator frequency l = inductor value solving this equation with our typical 5v to 3.3v applica- tion, we get: 17 066 200 2 28 .. . m = - khz h a pp peak inductor current at 10a load: 10 28 2 11 4 a a a += . . the inductor core must be adequate to withstand this peak current without saturating, and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss. note that the current may rise above this maximum level in circuits under current limit or under fault conditions in unlimited circuits; the inductor should be sized to withstand this additional current. input and output capacitors a typical ltc1430 design puts significant demands on both the input and output capacitors. under normal steady load operation, a buck converter like the ltc1430 draws square waves of current from the input supply at the switching frequency, with the peak value equal to the output current and the minimum value near zero. most of this current must come from the input bypass capacitor, since few raw supplies can provide the current slew rate to feed such a load directly. the resulting rms current flow in the input capacitor will heat it up, causing premature capacitor failure in extreme cases. maximum rms current occurs with 50% pwm duty cycle, giving an rms current applicatio s i for atio wu u u
10 ltc1430 internal circuitry v cc /pv cc2 ltc1430 (8-lead) pv cc1 m1 l1 m2 g1 g2 pv cc c out v out ltc1430 ?f07 + figure 7. 8-lead power supplies os-con part number 10sa220m (220 m f/10v) capacitors feature 2.3a allowable ripple current at 85 c and 0.035 w esr; three in parallel at the input and six at the output will meet the above requirements. input supply considerations/charge pump the 16-lead ltc1430 requires four supply voltages to operate: pv cc for the main power input, pv cc1 and pv cc2 for mosfet gate drive and a clean, low ripple v cc for the ltc1430 internal circuitry (figure 6). in many applica- tions, pv cc and pv cc2 can be tied together and fed from a common high power supply, provided that the supply voltage is high enough to fully enhance the gate of external mosfet m2. this can be the 5v system supply if a logic level mosfet is used for m2. v cc can usually be filtered with an rc from this same high power supply; the low quiescent current (typically 350 m a) allows the use of relatively large filter resistors and correspondingly small filter capacitors. 100 w and 4.7 m f usually provide ad- equate filtering for v cc . for both versions of the ltc1430, pv cc1 must be higher than pv cc by at least one external mosfet v gs(on) to fully enhance the gate of m1. this higher voltage can be provided with a separate supply (typically 12v) which should power up after pv cc , or it can be generated with a simple charge pump (figure 4). the charge pump consists of a 1n4148 diode from pv cc to pv cc1 and a 0.1 m f capacitor from pv cc1 to the switching node at the drain of m2. this circuit provides 2pv cc C v f to pv cc1 while m1 is on and pv cc C v f while m1 is off where v f is the on voltage of the 1n4148 diode. ringing at the drain of m2 can cause transients above 2pv cc at pv cc1 ; if pv cc is higher than 7v, a 12v zener diode should be included from pv cc1 to pgnd to prevent transients from damaging the circuitry at pv cc2 or the gate of m1. more complex charge pumps can be constructed with the 16-lead versions of the ltc1430 to provide additional voltages for use with standard threshold mosfets or very low pv cc voltages. a tripling charge pump (figure 5) can provide 2pv cc and 3pv cc voltages. these can be con- nected to pv cc2 and pv cc1 respectively, allowing stan- dard threshold mosfets to be used with 5v at pv cc or 5v logic level threshold mosfets to be used with 3.3v at pv cc . v cc can be driven from the same potential as pv cc2 , allowing the entire system to run from a single 3.3v supply. tripling charge pumps require the use of schottky diodes to minimize forward drop across the diodes at start-up. the tripling charge pump circuit will tend to rectify any ringing at the drain of m2 and can provide well more than 3pv cc at pv cc1 ; all tripling (or higher multiply- ing factor) circuits should include a 12v zener clamp diode d z to prevent overvoltage at pv cc1 . internal circuitry v cc ltc1430 (16-lead) pv cc2 pv cc1 m1 l1 m2 g1 g2 pv cc c out v out ltc1430 ?f06 + figure 6. 16-lead power supplies the 8-lead versions of the ltc1430 have the pv cc2 and v cc pins tied together inside the package (figure 7). this pin, brought out as v cc /pv cc2 , has the same low ripple requirements as the 16-lead part, but must also be able to supply the gate drive current to m2. this can be obtained by using a larger rc filter from the pv cc pin; 22 w and 10 m f work well here. the 10 m f capacitor must be very close to the part (preferably right underneath the unit) or output regulation may suffer. applicatio s i for atio wu u u
11 ltc1430 pensation components. in general, a smaller value induc- tor will improve transient response at the expense of ripple and inductor core saturation rating. minimizing output capacitor esr will also help optimize output transient response. see input and output capacitors for more information. compensation and transient response the ltc1430 voltage feedback loop is compensated at the comp pin; this is the output node of the internal g m error amplifier. the loop can generally be compensated prop- erly with an rc network from comp to gnd and an additional small c from comp to gnd (figure 8). loop stability is affected by inductor and output capacitor values and by other factors. optimum loop response can be obtained by using a network analyzer to find the loop poles and zeros; nearly as effective and a lot easier is to empirically tweak the r c values until the transient recovery looks right with an output load step. table 1 shows recommended compensation components for 5v to 3.3v applications based on the inductor and output capacitor values. the values were calculated using multiple paral- leled 330 m f avx tps series surface mount tantalum capacitors as the output capacitor. table 1. recommended compensation network for 5v to 3.3v application using multiple 330 m f avx output capacitors l1 ( m h) c out ( m f) r c (k w )c c ( m f) c1 (pf) 1 990 1.8 0.022 820 1 1980 3.6 0.01 470 1 4950 9.1 0.0047 150 1 9900 18 0.0022 82 2.7 990 3.6 0.01 470 2.7 1980 7.5 0.0047 220 2.7 4950 18 0.0022 82 2.7 9900 39 0.001 39 5.6 990 9.1 0.0047 150 5.6 1980 18 0.0022 82 5.6 4950 47 820pf 33 5.6 9900 91 470pf 15 10 990 18 0.0022 82 10 1980 39 0.001 39 10 4950 91 470pf 15 10 9900 180 220pf 10 output transient response is set by three major factors: the time constant of the inductor and the output capacitor, the more impact on overall transient recovery time than the third; unless the loop compensation is way off, more improvement can be had by optimizing the inductor and the output capacitor than by fiddling with the loop com- ltc1430 comp gnd sgnd ltc1430 ?f08 c1 c c r c figure 8. compensation pin hook-up soft-start and current limit the 16-lead versions of the ltc1430 include a soft-start circuit at the ss pin; this circuit is used both for initial start- up and during current limit operation. the soft-start and current limit circuitry is disabled in 8-lead versions. ss requires an external capacitor to gnd with the value determined by the required soft-start time. an internal 12 m a current source is included to charge the external capacitor. soft-start functions by clamping the maximum voltage that the comp pin can swing to, thereby control- ling the duty cycle (figure 9). the ltc1430 will begin to operate at low duty cycle as the ss pin rises to about 2v below v cc . as ss continues to rise, the duty cycle will increase until the error amplifier takes over and begins to regulate the output. when ss reaches 1v below v cc the ltc1430 will be in full operation. an internal switch shorts the ss pin to gnd during shutdown. the ltc1430 detects the output current by watching the voltage at i fb while m1 is on. the i lim amplifier compares this voltage to the voltage at i max (figure 10). in the on state, m1 has a known resistance; by calculating back- wards, the voltage generated at i fb by the maximum output current in m1 can be determined. as i fb falls below i max , i lim will begin to sink current from the soft-start pin, applicatio s i for atio wu u u
12 ltc1430 figure 10. current limit operation + i lim ltc1430 ltc1430 ?f10 r imax pv cc i max i fb ss c ss 12 m a 12 m a v cc 1k 0.1 m f u s a o pp l ic at i wu u i for atio causing the voltage at ss to fall. as ss falls, it will limit the output duty cycle, limiting the current at the output. eventually the system will reach equilibrium, where the pull-up current at the ss pin matches the pull-down current in the i lim amplifier; the ltc1430 will stay in this state until the overcurrent condition disappears. at this time i fb will rise, i lim will stop sinking current and the internal pull-up will recharge the soft-start capacitor, restoring normal operation. note that the i fb pin requires an external 1k series resistor to prevent voltage transients at the drain of m2 from damaging internal structures. the i lim amplifier pulls current out of ss in proportion to the difference between i fb and i max . under mild overload conditions, the ss pin will fall gradually, creating a time delay before current limit takes effect. very short, mild overloads may not trip the current limit circuit at all. longer overload conditions will allow the ss pin to reach a steady level, and the output will remain at a reduced voltage until the overload is removed. serious overloads will generate a larger overdrive at i lim , allowing it to pull ss down more quickly and preventing damage to the output components. the i lim amplifier output is disabled when m1 is off to prevent the low i fb voltage in this condition from activating the current limit. it is re-enabled a fixed 170ns after m1 turns on; this allows for the i fb node to slew back high and the i lim amplifier to settle to the correct value. as the ltc1430 goes deeper into current limit, it will reach a point where the m1 on-time needs to be cut to below 170ns to control the output current. this conflicts with the mini- mum settling time needed for proper operation of the i lim amplifier. at this point, a secondary current limit circuit begins to reduce the internal oscillator frequency, length- ening the off-time of m1 while the on-time remains con- stant at 170ns. this further reduces the duty cycle, allow- ing the ltc1430 to maintain control over the output current. under extreme output overloads or short circuits, the i lim amplifier will pull the ss pin more than 2v below v cc in a single switching cycle, cutting the duty cycle to zero. at this point all switching stops, the output current decays through m2 and the ltc1430 runs a partial soft-start cycle and restarts. if the short is still present the cycle will repeat. peak currents can be quite high in this condition, but the average current is controlled and a properly designed circuit can withstand short circuits indefinitely with only moderate heat rise in the output fets. in addi- tion, the soft-start cycle repeat frequency can drop into the low khz range, causing vibrations in the inductor which provide an audible alarm that something is wrong. ltc1430 ltc1430 ?f09 12 m a c ss comp ss fb v cc figure 9. soft-start clamps comp pin
13 ltc1430 u s a o pp l ic at i wu u i for atio oscillator frequency the ltc1430 includes an onboard current controlled oscillator which will typically free-run at 200khz. an internal 20 m a current is summed with any current in or out of the freqset pin (pin 11), setting the oscillator fre- quency to approximately 10khz/ m a. freqset is internally servoed to the ltc1430 reference voltage (1.26v). with freqset floating, the oscillator is biased from the internal 20 m a source and runs at 200khz. connecting a 50k resistor from freqset to ground will sink an additional 25 m a from freqset, causing the internal oscillator to run at approximately 450khz. sourcing an external 10 m a current into freqset will cut the internal frequency to 100khz. an internal clamp prevents the oscillator from running slower than about 50khz. tying freqset to v cc will cause it to run at this minimum speed. shutdown the ltc1430 includes a low power shutdown mode, controlled by the logic at the shdn pin. a high at shdn allows the part to operate normally. a low level at shdn stops all internal switching, pulls comp and ss to ground internally and turns m1 and m2 off. in shutdown, the ltc1430 itself will drop below 1 m a quiescent current typically, although off-state leakage in the external mosfets may cause the total pv cc current to be some- what higher, especially at elevated temperatures. when shdn rises again, the ltc1430 will rerun a soft-start cycle and resume normal operation. holding the ltc1430 in shutdown during pv cc power up removes any pv cc1 sequencing constraints. layout considerations grounding proper grounding is critical for the ltc1430 to obtain specified output regulation. extremely high peak currents (as high as several amps) can flow between the bypass capacitors and the pv cc1 , pv cc2 and pgnd pins. these currents can generate significant voltage differences be- tween two points that are nominally both ground. as a general rule, gnd and pgnd should be totally separated on the layout, and should be brought together at only one point, right at the ltc1430 gnd and pgnd pins. this helps minimize internal ground disturbances in the ltc1430 by keeping pgnd and gnd at the same potential, while preventing excessive current flow from disrupting the operation of the circuits connected to gnd. the pgnd node should be as compact and low impedance as pos- sible, with the negative terminals of the input and output capacitors, the source of m2, the ltc1430 pgnd node, the output return and the input supply return all clustered at one point. figure 11 is a modified schematic showing the common connections in a proper layout. note that at 10a current levels or above, current density in the pc board itself can become a concern; traces carrying high currents should be as wide as possible. output voltage sensing the ltc1430 provides three pins for sensing the output voltage: sense + , sense C and fb. sense + and sense C connect to an internal resistor divider which is connected to fb. to set the output of the ltc1430 to 3.3v, connect sense + to the output as near to the load as practical and connect sense C to the common gnd/pgnd point. note that sense C is not a true differential input sense input; it is just the bottom of the internal divider string. connecting sense C to the ground near the load will not improve load regulation. for any other output voltage, the sense + and sense C pins should be floated and an external resistor string should be connected to fb (figure 12). as before, connect the top resistor (r1) to the output as close to the load as practical and connect the bottom resistor (r2) to the common gnd/pgnd point. in both cases, connecting the top of the resistor divider (either sense + or r1) close to the load can significantly improve load regulation by compensating for any drops in pc traces or hookup wires between the ltc1430 and the load. power component hook-up/heat sinking as current levels rise much above 1a, the power compo- nents supporting the ltc1430 start to become physically large (relative to the ltc1430, at least) and can require special mounting considerations. input and output ca- pacitors need to carry high peak currents and must have low esr; this mandates that the leads be clipped as short as possible and pc traces be kept wide and short. the
14 ltc1430 u s a o pp l ic at i wu u i for atio figure 11. typical schematic showing layout considerations v out r1 nc nc r2 ltc1430 ?f12 ltc1430 sense + fb sense figure 12. using external resistors to set output voltages + + + ltc1430 ?f11 3.3v 2.7 m h/15a total 1980 m f (330 m f 6.3v 6) m1a* m2* pv cc1 i max freqset gnd pgnd shdn comp nc ss pv cc2 v cc pgnd gnd r c 7.5k 0.1 m f 1 m f 0.1 m f c c 4700pf c1 220pf c ss 0.01 m f 4.7 m f 35v 100 w g1 i fb g2 fb sense + nc nc ltc1430 sense gnd pgnd * motorola mtd20n03hl 1n4148 5v m1b* total 880 m f (220 m f 10v 4) power inductor will generally be the most massive single component on the board; it can require a mechanical hold- down in addition to the solder on its leads, especially if it is a surface mount type. the power mosfets used require some care to ensure proper operation and reliability. depending on the current levels and required efficiency, the mosfets chosen may be as large as to-220s or as small as so-8s. high efficiency circuits may be able to avoid heat sinking the power devices, especially with to-220 type mosfets. as an example, a 90% efficient converter working at a steady 3.3v/10a output will dissipate only (33w/90%) ? 10% = 3.7w. the power mosfets generally account for the majority of the power lost in the converter; even assuming that they consume 100% of the power used by the converter, thats only 3.7w spread over two or three devices. a typical so-8 mosfet with a r on suitable to provide 90% efficiency in this design can commonly dissipate 2w when soldered to an appropriately sized piece of copper trace on a pc board. slightly less efficient or higher output current designs can often get by with standing a to-220 mosfet straight up in an area with some airflow; such an arrangement can dissipate as much as 3w without a heat sink. designs which must work in high ambient temperatures or which will be routinely overloaded will generally fare best with a heat sink.
15 ltc1430 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. package descriptio u dimensions in inches (millimeters) unless otherwise noted. n8 1098 0.100 (2.54) bsc 0.065 (1.651) typ 0.045 ?0.065 (1.143 ?1.651) 0.130 0.005 (3.302 0.127) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 0.125 (3.175) min 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 +0.035 0.015 +0.889 0.381 8.255 () 12 3 4 87 6 5 0.255 0.015* (6.477 0.381) 0.400* (10.160) max *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.254mm) n16 1098 0.020 (0.508) min 0.125 (3.175) min 0.130 0.005 (3.302 0.127) 0.065 (1.651) typ 0.045 ?0.065 (1.143 ?1.651) 0.018 0.003 (0.457 0.076) 0.100 (2.54) bsc 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 +0.035 0.015 +0.889 0.381 8.255 () *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.254mm) 0.255 0.015* (6.477 0.381) 0.770* (19.558) max 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 n8 package 8-lead pdip (narrow 0.300) (ltc dwg # 05-08-1510) n package 14-lead pdip (narrow 0.300) (ltc dwg # 05-08-1510)
16 ltc1430 ? linear technology corporation 1995 1430fa lt/tp 0500 2k rev a ? printed in usa related parts part number description comments ltc1530 high power synchronous step-down controller so-8 with current limit. no r sense required ltc1625 no r sense tm current mode synchronous step-down controller above 95% efficiency, needs no r sense , 16-lead ssop package fits so-8 footprint ltc1628 dual high efficiency 2-phase synchronous step-down controller constant frequency, standby 5v and 3.3v ldos, 3.5v v in 36v ltc1703 dual 550khz synchronous 2-phase switching regulator controller ltc1702 with 5-bit mobile vid for mobile pentium ? processor with mobile vid systems ltc1706-81 vid voltage programmer adds 5-bit mobile vid to 0.8v referenced switching regulators ltc1709 2-phase, 5-bit desktop vid synchronous step-down controller current mode, v in to 36v, i out up to 42a ltc1736 synchronous step-down controller with 5-bit mobile vid control fault protection, powergood, 3.5v to 36v input, current mo de ltc1753 5-bit desktop vid programmable synchronous 1.3v to 3.5v programmable output using internal 5-bit dac switching regulator ltc1873 dual synchronous switching regulator with 5-bit desktop vid 1.3v to 3.5v programmable core output plus i/o output ltc1929 2-phase, synchronous high efficiency converter current mode ensures accurate current sensing, v in up to 36v, i out up to 40a no r sense is a trademark of linear technology corporation. pentium is a registered trademark of intel corporation. package descriptio u dimensions in inches (millimeters) unless otherwise noted. 0.016 ?0.050 (0.406 ?1.270) 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) so8 1298 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) typ 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) bsc 1 2 3 4 0.150 ?0.157** (3.810 ?3.988) 8 7 6 5 0.189 ?0.197* (4.801 ?5.004) 0.228 ?0.244 (5.791 ?6.197) dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** 0.016 ?0.050 (0.406 ?1.270) 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) s16 1098 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) typ 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) bsc 1 2 3 4 5 6 7 8 0.150 ?0.157** (3.810 ?3.988) 16 15 14 13 0.386 ?0.394* (9.804 ?10.008) 0.228 ?0.244 (5.791 ?6.197) 12 11 10 9 dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** s8 package 8-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) s package 16-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com

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